The invention relates to an integrated memory having plate line segments.
A memory of this type is described in U.S. Pat. No. 5,424,976 A. This memory is a ferroelectric memory of the FRAM type (ferroelectric random access memory). The memory cells of an FRAM are constructed in exactly the same way as memory cells of DRAMs (dynamic random access memories). In other words, each memory cell has a selection transistor and a storage capacitor, but in contrast to a DRAM, the storage capacitor has a ferroelectric dielectric.
The method of operation of such a memory will be roughly explained below with reference to the abovementioned U.S. Pat. No. 5,424,976 A. The memory cells are arranged at crossover points of bit lines, word lines and plate line segments. The selection of a plurality of memory cells assigned to a common column, which in each case has a plurality of the bit lines, is effected by activation of the associated word line and pulsing of the associated plate line segment. In this case, the plate line segments are connected via transistors functioning as switching elements to control lines, whose potential depends on column addresses present at the memory. The gates of the switching transistors are connected to that word line which is assigned to the memory cells of the respective plate line segment. It follows from this that the plate line is connected to the corresponding plate line segment when the associated word line is activated for selection of the corresponding memory cells. The switching transistor is in the on state in this case. Otherwise, the switching transistor is in the off state, so that the corresponding plate line segment is decoupled from the control line which has a defined potential. In the decoupled case, the plate line segments connected to one of the electrodes of the storage capacitors float, that is to say they do not have a defined potential.
The invention is based on the object of specifying an integrated memory of the type described which is less susceptible to faults than known memories.
The integrated memory according to the invention has driver units, via which the column select lines are connected to the plates line segments and which, as a function of the potential of the associated column select lines and the word addresses on the plate line segments connected to them, generate potentials which have defined values for each operating state of the memory.
The aforementioned features prevent the plate line segments from floating. Interfering influences on the plate line segments on account of crosstalk of lines, for example word lines, running parallel to the plate line segments are thereby prevented. Crosstalk can occur, in particular, in large scale integrated memories, in which the distances between the corresponding lines are particularly small. Since the potential of the plate line segments is always held at defined values both in the event of a selection of the memory cells connected to them and when the memory cells connected to them are not selected, there is no, or at least only very little, influencing of the potential of the segments on account of crosstalk. In the case of the memory according to the invention, the presence of defined potential values on the plate line segments in each operating state of the memory is achieved by the provision of the driver units. A driver unit generates an output signal which always assumes defined values as a function of input signals of the driver unit. U.S. Pat. No. 5,424,976 cited further above exhibits no driver units of this type, but merely switching transistors, which, in the off state, cause the plate line segments connected to them to float.
According to an advantageous development, the plate line segments run parallel to the bit lines and the memory has multiplexers each arranged electrically between one of the driver units and two of the plate line segments, the multiplexers connecting the driver units to one of the two associated plate line segments as a function of word addresses. In this development, then, one of the driver units is in each case assigned to two of the plate line segments via the associated multiplexer. Therefore, only a smaller number of driver units are necessary than if a separate driver unit were in each case provided per plate line segment. It goes without saying that a driver unit can also be assigned to a larger number of plate line segments via a corresponding multiplexer.
According to another development of the invention, the plate line segments are arranged in a first wiring plane and are isolated from one another by isolating regions in the direction of the word lines. Furthermore, line-shaped structures are provided which are arranged in a second wiring plane perpendicularly to the word lines at regular distances from one another. In this case, the bit lines are formed by those line-shaped structures which are arranged parallel to the plate line segments running in the first wiring plane, while those line-shaped structures which are arranged parallel to the isolating regions running in the first wiring plane are dummy structures connected to none of the memory cells.
In this development, the line-shaped structures arranged at regular distances in the second wiring plane ensure a uniform and thus technologically unproblematic production. In this case, however, not every line-shaped structure is utilized as bit line, but rather only those line-shaped structures which are assigned an associated plate line segment in the first wiring plane. The remaining line-shaped structures, which do not form bit lines, serve merely for simplifying the production process and are therefore what are called xe2x80x9cdummy structuresxe2x80x9d, which serve no electrical function at all in the completed integrated circuit.
In the development just described, it is particularly advantageous if there is arranged in the second wiring plane, parallel to each isolating region, in each case precisely a single one of the dummy structures, which isolates two groups of adjacent bit lines from one another. This solution thus provides relatively narrow isolating regions between the plate line segments, which are assigned, in the second wiring plane, only one of the line-shaped structures arranged at regular distances from one another. This results in the integrated memory having a construction that is as compact as possible.